This invention relates to channel-stop implants under thick-field isolation regions formed on triple-well structures to provide electrical insulation between N-channel field-effect devices.
Certain Flash Electrically-erasable, Programmable Read-Only-Memory (Flash EPROM) arrays are formed using triple-well structures. A compensation method is used to form a typical triple-well structure in a silicon substrate of P-type conductivity. The first step is to implant phosphorous in the substrate, then perform a tank-drive step to form wells of N-type conductivity (N-wells). The next step is to implant boron, followed by a second tank-drive step, to create isolated wells of P-type conductivity (P-wells) inside the N-wells. Therefore, the P-wells contain both boron and phosphorous, with boron predominating. The triple-well structure is completed by forming source/drain diffusions of N-type conductivity in the P-wells. The source/drain diffusions are a part of N-channel devices such as memory cells or peripheral transistors. Memory cells and many of the transistors of peripheral circuits require electrical separation between these source/drain diffusions.
In general, EPROMs of all types use boron channel-stop implants under grown thick-field isolation regions to provide electrical isolation between N-channel memory cells and between N-channel peripheral transistors. However, use of boron channel-stop implants under thick-field isolation regions formed on triple-well structures causes a unique problem. The segregation coefficient M, which is defined as the ratio of impurity concentration in silicon over impurity concentration in silicon dioxide, is less than one for boron and is greater than one for phosphorous. This results in boron depletion in the silicon immediately under a thick-field isolation region grown in a P-well structure and results in a phosphorous accumulation in the silicon immediately under a thick-field isolation region grown in a N-well structure. That is, during growth of the oxide forming the thick-field isolation regions, boron is depleted and simultaneously phosphorous is accumulated immediately under the thick-field isolation region. As a result, the phosphorous concentration overcomes the boron concentration in that location, creating a N-type region that is responsible for current leakage, possibly a short-circuit, under the thick-field isolation regions.
Using boron as a channel-stop implant before growing the thick-field isolation regions is one conventional method for preventing current leakage under those isolation regions in a P-well structure. In that conventional method, boron is implanted into the selected P-well sites before growing the oxide forming the thick-field isolation regions. The boron implant is made for the purpose of increasing the threshold voltage for current flow under the N+ thick-field isolation region. When a boron channel stop is implanted prior to growing the oxide forming the thick-field isolation regions in a triple-well structure, some boron diffuses deeper into silicon and some diffuses into the thick-field isolation region during the oxide growth. Therefore, a much higher dosage of boron is needed to overcome the phosphorous accumulation and to maintain as P-type the silicon region underlying the thick-field isolation region. However, a high-boron dose channel-stop implant has an adverse effect on the transistor-junction breakdown voltages under the thick-field isolation regions.
On the other hand, a second prior-art method uses a single high-energy channel-stop implant performed through the thick-field isolation regions, the implant performed after the oxide growth forming those regions. The high-energy implant is also intended to stop formation of a conductive channel in the silicon immediately under the thick-field isolation regions. However, when using this second prior-art method, there is a problem in placing a sufficient concentration of boron at the correct depth under the thick-field isolation regions. In a part of the detailed discussion below, high-energy channel-stop implants are simulated for thick-field isolation regions built in an isolated P-well formed inside a N-well. Simulation results indicate that if only one high-energy implant is performed, a precise channel-stop implant energy is needed to place the correct amount of boron under the thick-field isolation regions to stop channel conduction and source-to-drain shorts.
There is a great and continuing need to shrink the size of integrated-circuit devices in both the horizontal and the vertical directions. That need includes shrinking the size of thick-field isolation regions to allow placement of more transistor devices on a silicon substrate. There is also a great and continuing need for thick-field isolation regions that are not only small and thin, but that are easy to manufacture and easy to shrink in size as minimum photolithographic capabilities become available. Preferably, the channel-stop implant method used to accomplish these goals should, at the same time, be independent of process variations. Those variations include:
1) minor changes in energy and dosage of the channel-stop implants, and PA1 2) variation in the thickness of the thick-field isolation regions, including non-uniform thickness resulting from wet de-glazing steps.